The present invention provides a method for fabricating a thin film transistor, and more particularly to a method for fabricating a thin film transistor-liquid crystal display (TFT-LCD).
Please refer to FIGS. 1(a) to (e). For fabricating a typical TFT-LCD, five photolithography and etch processes are required. A gate conducting layer is formed on an insulating substrate 10 and a first photolithography and etch process is performed to form a gate conducting structure 11, as shown in FIG. 1(a). A gate insulator layer 12, a channel layer 13, and an etched-stop layer are formed in sequence, and the etched-stop layer is etched by a second photolithography and etch process to form an etched-stop structure 14, as shown in FIG. 1(b). In addition, a source/drain layer and a data line layer are formed in sequence, and a third photolithography and etch process is performed to form a source/drain structure 15 and a data line structure 16, as shown in FIG. 1(c). A passivation 17 is formed and a fourth photolithography and etch process is performed to define a contact window structure 18, as shown in FIG. 1(d). Finally, a transparent electrode layer is formed and a fifth photolithography and etch process is performed to form a transparent pixel electrode area 19, as shown in FIG. 1(e).
However, there is a problem that the five photolithography and etch processes are complex, time consuming and costly. Furthermore, damage due to the photolithography and etch processes may occur, thereby deteriorating reliability and yield of the fabricating process.
Therefore, the present invention provides a method for fabricating a TFT-LCD to overcome the foresaid drawbacks.
There is an object of the present invention to provide a method for fabricating a thin film transistor (TFT).
In accordance with the present invention, the method includes steps of a) providing an insulation substrate, b) forming a conductive layer on the insulation substrate, c) defining the conductive layer as a gate conducting structure by a first photolithography and etch process, d) forming a gate insulation layer, a channel layer, a junction layer, a source/drain layer and a data line layer in sequence, and etching the data line layer, the source/drain layer and the junction layer by a second photolithography and etch process to form a source/drain structure and a data line structure, and e) heat-treating the junction layer to reduce resistance between the source/drain structure and the channel layer.
Preferably, the channel layer is formed by intrinsic semiconductor, and the source/drain layer is made of highly doped semiconductor. The intrinsic semiconductor is intrinsic amorphous silicon, and the highly doped semiconductor is highly doped amorphous silicon.
Preferably, the material of the junction layer is one of a highly doped germanium layer and a highly doped silicon-germanium layer.
In addition, the junction layer has a thickness ranged from about 100 to 200 angstrom. The step of heat-treating the junction layer is an annealing process performed at 350 to 550xc2x0 C. for 2 to 4 hours.
In addition, the junction layer is a silicidable metal layer. Preferably, the silicidable metal is one selected from a group consisting of chromium, nickel and platinum. The silicidable metal layer has a thickness ranged from about 50 to 100 angstrom.
Preferably, the step of heat-treating said junction layer is an annealing process performed at 230xc2x0 C. for 1 hour.
There is another object of the present invention to provide a method for fabricating a thin film transistor-liquid crystal display (TFT-LCD)
In accordance with the present invention, the method includes steps of a) providing an insulation substrate, b) forming a conductive layer on the insulation substrate, c) defining the conductive layer as a gate conducting structure by a first photolithography and etch process, d) forming a gate insulation layer, a channel layer, a junction layer, a source/drain layer and a data line layer in sequence, and etching the data line layer, the source/drain layer and the junction layer by a second photolithography and etch process to form a source/drain structure and a data line structure, e) forming a passivation and defining a contact window on the passivation by a third photolithography and etch process, f) forming a transparent electrode layer and defining a transparent pixel electrode region by a fourth photolithography and etch process, and g) heat-treating the junction layer to reduce resistance between the source/drain structure and the channel layer.
Preferably, the channel layer is formed by intrinsic semiconductor, and the source/drain layer is formed by highly doped semiconductor. The intrinsic semiconductor is intrinsic amorphous silicon, and the highly doped semiconductor is highly doped amorphous silicon.
Preferably, the material of the junction layer is one of a highly doped germanium layer and a highly doped silicon-germanium layer.
Preferably, the junction layer has a thickness ranged from about 100 to 200 angstrom. The step of heat-treating is a first annealing process performed at 230xc2x0 C. for 1 hour. The junction layer is a silicidable metal layer having a thickness ranged from about 50 to 100 angstrom.
In accordance with the present invention, the silicidable metal is one selected from a group consisting of chromium, nickel and platinum.
In addition, the transparent pixel electrode is made of indium tin oxide. Furthermore, the first annealing process is combined with a second annealing process performed on the indium tin oxide.
The present invention may best be understood through the following descriptions with reference to the accompanying drawings, in which: